In recent years, the performance of a component such as a CPU constituting an information processing system such as a server or a computer, especially the bandwidth of the component is greatly increasing. Therefore, in order to increase the total bandwidth of the entire information processing system, the speed of a transceiver circuit transmitting and receiving data between chips such as the CPU and between a plurality of elements or circuit blocks within the chip needs to be improved. Further, the speed of a transceiver circuit transmitting and receiving data between boards or between cases also needs to be improved. In the transceiver circuit performing a high speed data communication, a signal equalization circuit (equalizer) is utilized so as to compensate for a degradation of data signal occurring in a transmission line.
There is a speculative type decision feedback equalizer (DFE) as a type of equalizer. The DFE applies an offset voltage to the data signal, for which a comparator has not yet made a determination, by an amount of the deterioration of signal due to an Inter-Symbol Interference (ISI) generated by the previous data so as to compensate for the deterioration of signal due to the ISI. In the DFE, since the data signal is required to be compensated for each bit, a selection circuit, it may be indicated as MUX, selecting a determination result of the comparator is required to select the signal each at a time for 1 bit width of data (1 unit interval (UI)). Accordingly, a delay time of a signal route for controlling the MUX is required to be less than 1UI of data.
The speculative type DFE circuit applies a plurality of types of offset voltages as many as the types of values capable of being taken by the data to the signal in advance, and selects the signal to which the offset voltage corresponding to the determined data is applied at the time when the data is determined. Accordingly, an unnecessary processing is caused, but a time required for a processing of giving the offset voltage may be reduced as compared to a case where the offset voltage is given after the data is determined.
A data transmission scheme of a multi-level modulation is used in order to increase a data transmission amount per unit time. As for a configuration of the speculative type DFE with the multi-level modulation, a method in which a decoder is used is known. For example, when a transmission scheme is a four-level pulse amplitude modulation (PAM4) using a pulse amplitude modulation (PAM), the MUX needs to know “0” or “1” of a high order bit and “0” or “1” of a low order bit of the data in order to select a single signal from four input signals. Accordingly, the MUX is controlled by two control signals. Here, since three comparators are required in order to determine four-level amplitude information in PAM4, three MUXs are required in the DFE for PAM4. Accordingly, a decoder for generating two signals that control the MUXs by using three signals output from the MUXs is used.
However, since the decoder not required in the speculative DFE using two-level modulation is added, a delay time of the signal route for controlling the MUX is increased by a delay time for the decoder. As a result, an operation speed of the DFE becomes slower and it becomes difficult to further increase the data rate.
Related techniques are disclosed in, for example, Japanese Laid-open Patent Publication No. 2012-039267, International Publication Pamphlet No. WO 2009/113462, and Japanese Laid-open Patent Publication No. 2011-244284.
Related techniques are also disclosed in a non-patent literature, i.e., “A 4PAM/2PAM COAXIAL CABLE RECEIVER ANALOG FRONT-END TARGETING 40G B/S IN 90-NM CMOS”, Peter Park, A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Computer Engineering, University of Toronto.